The invention relates to a semiconductor memory device having a plurality of memory cells which are selectively driven in response to a drive signal.
With integrated semiconductor memory devices (IC memory), signal propagation delay of the word line must be decreased and the voltage of the bit line signal read from the memory cell must be maintained stable at a sufficiently high level in order to increase speed and the degree of integration as well as in order to decrease the power consumption of the device. In order to accomplish this, the IC memory is divided into a plurality of memory cell blocks and the memory cells are selected by the individual blocks.
FIG. 1 shows the prior art IC memory device which has a plurality of memory blocks 11 each comprised of a plurality of memory cells. As can be seen from one of the memory blocks in the drawing, word lines 12 and bit lines 13 are provided for each cell in order to select a memory cell. Although not shown in the drawing, each memory cell is located at an intersection of each word and bit line 12, 13 so as to be coupled to each. Also, this IC memory includes row decoders 14, which are provided for each block 11 and which select a word line 12 in each memory block 11 based on a row address signal and further includes column decoders 15 which are also provided for each pair of blocks contiguous in the horizontal direction, for example, and which select bit lines 13 in each block 11 based on a column address signal.
In this case, one row decoder 14 is provided for each memory block 11. Similarly, with column decoders 15, one decoder may be provided for each pair of memory blocks 11 that are vertically contiguous, for example. Sense amps 16 amplify the data read from or written into at least one memory cell selected by row decoder 14 and column decoder 15. In other words, when sense amps 16 read out data, they amplify and hold data read out of the corresponding memory cells, and when they write in data, they hold the data that is to be written into the corresponding memory cells.
Drive signal generator 17 supplies drive signal .phi.1 to row decoder 14. If the memory is dynamic random access memory (dRAM), drive signal generator 17 generates signal .phi.1 in response to changes in the row address strobe signal RAS, which is provided simultaneously with the row address signal.
FIG. 2 is a detailed circuit diagram of a row decoder 14 of the prior art IC memory. In the description below, the MOS transistors are all enhancement-type n-channel transistors.
Transistor 22 is provided between power source terminal Vcc and decoder signal output line 21 and precharge signal .phi.2 is supplied to the gate of this transistor. A plurality of transistors 23 are provided in parallel between decode signal output terminal 21 and reference potential source terminals Vss. These transistors 23 are for decoding the row address signals and a bit signal expressing a special combination of row address signals is supplied to the gate of each.
The gate of transistor 24 is connected to decode signal output line 21. Signal .phi.1 generated by drive signal generator 17 is supplied to one end of the current path of transistor 24 and the other end is connected to the corresponding word line 12. That is to say, with this kind of row address decoder 14, first a precharge signal .phi.2 is supplied to the gate of transistor 22 to charge the decode signal output line 21 to level "1". Next, when the row address signal is generated, drive signal generator 17 generates signal .phi.1 based on the row address strobe signal RAS as well as turns off all of transistors 23 through only one row address decoder 14. Then, decode signal output line 21 is kept at the "1" level and transistor is turned on.
Accordingly, the corresponding word line 12 is charged to "1" level by the drive signal .phi.1 supplied to transistor 24. After this, all the memory cells connected to this word line 12 are accessed and based on the column signals supplied after this, column decoder 15 selects a special bit line 13 to thereby select at least one memory cell in one memory block 11. Then, reading out or writing in of data is performed for this memory cell.
At this time, in the other row address decoder 14, at least one of transistors 23 is turned on and this caused decode signal output line 21 to be charged to a "0" level. Accordingly, transistor 24 is turned off and drive signal .phi.1 is not supplied to the corresponding word line 12.
With this kind of prior art memory, drive signal .phi.1, which is used for selecting word lines 12, is supplied in parallel to all of row decoders 14, which each determine whether the word lines 12 will be charged to level "1" based on the individual row address signals. With this kind of memory there is no problem if there are few memory cells and there are few row decoders 14 to which signal .phi.1 must be supplied.
With the recent drastic increases in memory integration together with an increase in the number of memory cells, however, the number of row decoders 14 has increased, resulting in an increase in the number of wires between row decoders 14 and drive signal generator 17 and in the length of those wires. The stray capacitance associated with these wires is a multiple of the parasitic capacitance associated with one word line 12 to be driven in the end by drive signal .phi.1. Furthermore, the increase in resistance of the wire results in great attenuation of drive signal .phi.1 before it charges word line 12 to level "1". Accordingly, in the past, much time was required until the selected word line 12 rose to a sufficiently high level to be considered level "1", which slowed down the operating speed.
In order to improve this operating speed, the current capacity of signal .phi.1 must be increased and, to do this, the element area of the transistors comprising drive signal generator 17 must be increased. This in turn results in an increase in chip area when the circuitry is integrated.